The present invention relates to module devices of semiconductor packages, and more particularly, to a module device composed of a plurality of stacked semiconductor packages.
Modern electronic products are developed toward requirements of multifunction, high electrical performance and high-speed operation, which can be complied by a multi chip module (MCM) semiconductor device incorporated with a plurality of chips.
A primary type of the MCM semiconductor device is to integrate a plurality of chips in a single semiconductor device. As shown in FIGS. 1a and 1b, a plurality of chips 11 are stacked on a substrate 10 (FIG. 1a), or a plurality of chips 21 are coplanarly mounted on a substrate 20 (FIG. 1b) in the MCM semiconductor device. This semiconductor device has a drawback that electrical and reliability tests can only be performed for the chips after completing the packaging or encapsulating process; in this case, if any chip fails in the tests, the whole semiconductor device fails to function and must be reworked or scraped, thereby increasing fabrication costs; this drawback is referred to as a KGD (known good die) problem.
As shown in FIG. 1c, U.S. Pat. No. 6,303,997 discloses another semiconductor device integrated with a plurality of chips in which a chip 31 and a semiconductor package 32 are mounted on and electrically connected to a substrate 30. During fabrication of the semiconductor device 3, the chip 31 is first electrically connected to an upper surface of the substrate 31 by bonding wires 311 and subject to tests. After the chip 31 is determined to properly function, the fabricated semiconductor package 32 is mounted to the substrate 30 by surface mount technology (SMT) and electrically connected to the substrate 30 via solder balls 321. Finally, the entire semiconductor device 3 is tested so as to solve the foregoing KGD problem of the above conventional MCM semiconductor device. However, a plurality of bond fingers and ball pads have to be formed on the upper surface of the substrate 30 in the semiconductor device 3, for use to electrically connect the chip 31 and semiconductor package 32 to the substrate 30. This not only restricts trace routability on the substrate 30, but also requires high-density fabrication processes for making build-up substrates, thereby undesirably increasing fabrication costs.
U.S. Pat. No. 5,783,870 discloses a further example of a semiconductor device incorporated with a plurality of chips in which a plurality of semiconductor packages are integrated to form a single module semiconductor device. As shown in FIG. 1d, this module semiconductor device 4 allows a second semiconductor package 40b to be stacked on a first semiconductor package 40a, wherein the second semiconductor package 40b is attached and electrically connected via its plurality of solder balls 411b to an upper surface of a substrate 41a of the first semiconductor package 40a, and a third semiconductor package 40c is stacked in a similar way on the second semiconductor package 40b. In this module semiconductor device, each semiconductor package can be individually subject to required tests; after passing the tests, the semiconductor packages are then stacked on each other; further, the module semiconductor device uses conventional substrates to solve the KGD problem usually encountered by the MCM device. However, in the package-stack structure of the module semiconductor device, an upper semiconductor package can only be mounted and electrically connected to a substrate of a lower semiconductor package at area outside a chip attach region for accommodating a chip in the lower semiconductor package; that is, the electrically-connecting area on the substrate of the lower semiconductor package is limited and thus affects trace routability of the substrate, whereby quantity and arrangement of input/output (I/O) connections of the upper semiconductor package would also be restricted, thereby adversely affecting design flexibility of the entire semiconductor device.
Therefore, the problem to be solved herein is to improve integration of a semiconductor device through the use of simple fabrication processes and reduced fabrication costs.
A primary objective of the present invention is to provide a module device composed of a plurality of stacked semiconductor packages and a method for fabricating the module device, so as to enhance reliability and workability for fabrication of the module device.
Another objective of the invention is to provide a module device composed of a plurality of stacked semiconductor packages and a method for fabricating the module device, so as to reduce complexity of fabrication processes and production costs for the module device.
A further objective of the invention is to provide a module device composed of a plurality of stacked semiconductor packages and a method for fabricating the module device, so as to improve trace routability and design flexibility of the module device for incorporating a plurality of semiconductor packages in the module device.
In accordance with the foregoing and other objectives, the present invention proposes a module device composed of a plurality of stacked semiconductor packages, comprising: a first semiconductor package; and at least a second semiconductor package stacked on and electrically connected to the first semiconductor package.
The first semiconductor package comprises: a chip carrier; at least a chip mounted on the chip carrier; a plurality of first conductive elements for electrically connecting the chip to the chip carrier; a circuit board having a top surface and a bottom surface, and mounted above the chip; a plurality of second conductive elements disposed on the bottom surface of the circuit board, for supporting and electrically connecting the circuit board to the chip carrier; an encapsulant formed between the chip carrier and the circuit board, for encapsulating the chip and the first and second conductive elements, allowing the top surface of the circuit board to be exposed to outside of the encapsulant; and a plurality of third conductive elements for electrically connecting the chip to an external device.
The second semiconductor package is electrically connected to the exposed top surface of the circuit board of the first semiconductor package by means of the first conductive elements, and integrated with the first semiconductor package to thereby form a module device of stacked semiconductor packages.
A method for fabricating the module device according to the invention comprises the steps of: preparing a chip carrier and mounting at least a chip on the chip carrier, allowing the chip to be electrically connected to the chip carrier by a plurality of first conductive elements; providing a circuit board having a top surface and a bottom surface, and formed a plurality of second conductive elements on the bottom surface of the circuit board; mounting the circuit board above the chip carrier incorporated with the chip, and electrically connecting the circuit board to the chip carrier by the second conductive elements; forming an encapsulant between the chip carrier and the circuit board for encapsulating the chip and the first and second conductive elements, allowing the top surface of the circuit board to be exposed to outside of the encapsulant, so as to fabricate a first semiconductor package; mounting a plurality of third conductive elements on the chip carrier, for electrically connecting the first semiconductor package to an external device; and electrically connecting at least a second semiconductor package to the top surface of the circuit board of the first semiconductor package.
With the circuit board being incorporated in the first semiconductor package by means of the second conductive elements and the encapsulant formed between the circuit board and the chip carrier, it provides preferable reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package. Moreover, the top surface of the circuit board exposed to outside of the first semiconductor package or encapsulant can be entirely used for mounting the second semiconductor package thereon, thereby improving trace routability or layout for accommodating more electronic elements.